1. Field of the Invention
The present invention relates to a gas etchant composition and a method for simultaneously etching silicon oxide and polysilicon, and a method for manufacturing semiconductor devices using the same. More particularly, the present invention relates to a gas etchant composition for simultaneously etching silicon oxide and polysilicon during an etch-back process of manufacturing a capacitor for a semiconductor memory device, an etching method thereof, and a method for manufacturing a semiconductor device using the same.
2. Background of the Related Art
Currently, due to widespread usage of computers in information media, memory devices are being developed which provide semiconductor devices with higher memory storage capacity and faster operating speeds. To this end, the current technology in the art is focused on developing and realizing memory devices having a high degree of integration, response speed, and reliability. Conventionally, dynamic random access memory (DRAM) devices, which have a high memory capacity and random open input/output functions, are widely used as semiconductor memory devices.
DRAM devices generally comprise a memory cell having at least one transistor and a capacitor to charge/discharge electrical charges for input/output functioning of information data. Further, DRAM devices conventionally comprise a memory cell region for storing large information data and peripheral circuits for input/out functioning of information data. To obtain a high integration in such DRAM devices comprising a capacitor, it is necessary to decrease the size of the cells, which results in decreased sizes and degree of margins of patterns formed on a semiconductor substrate. Consequently, the aspect ratio of the components which make up the substrate increases.
Conventionally, a stacked-capacitor cell having an electrode comprising polysilicon layers and a dielectric film made from a silicon nitride layer is widely used as a DRAM cell for Mb DRAMs. However, it is difficult to obtain an adequate cell capacitance with the capacitor cell having such a simple stacked structure in highly integrated DRAMs. As such, tantalum oxide layers having a higher dielectric constant are utilized for the dielectric layers in place of silicon nitride layers, or the structure of the stacked-capacitors is changed to increase the effective area of the capacitors.
Generally, to increase the cell capacitance in DRAMs, the storage electrode is heightened to form a stacked-structure. However, in view of the very high integration of semiconductor devices, the size of the cells need to be decreased instead. Thus, in order to increase the cell capacitance, the critical distance between storage electrodes formed on the cells should be decreased or the height of the storage electrode should be increased. However, if the critical distance is decreased, an electrical bridge may form between adjacent storage electrodes, thereby causing a short. If the height of the storage electrode is increased the global step in the devices is also increased, which leads to decreased image margin during the photo-process, thereby causing shorts between the metal wirings in the subsequent processes.
To increase the effective area of the capacitors, a method of forming a rugged shape on the surface of polysilicon layers used for obtaining the storage electrode of capacitors has been suggested. The rugged shape is obtained by an etching process or by manipulating the manufacturing variables which control the process of growing polysilicon layers. A method of manufacturing a capacitor utilizing the above method of forming a rugged shape on the surface of polysilicon layers is described below.
First, a main storage electrode is formed at the surface of a semiconductor substrate, then a hemispherical grained (HSG) polysilicon layer is formed on the whole surface of the storage electrode, followed by an anisotropic etching process, which results in a rugged shaped storage electrode.
The above HSG polysilicon layer is formed on the surface of the main storage electrode by using helium diluted SiH.sub.4 gas under a pressure of 1.0 Torr and at a temperature of 550.degree. C. By utilizing such an HSG polysilicon layer, the cell capacitance can be significantly increased, since the effective area can be increased two to three times over the conventional polysilicon layer not having the rugged shape structure.
As shown by the above, the current technology of increasing the cell capacitance of DRAMs utilizes the method of manufacturing a capacitor having a stacked structure and forming an HSG silicon layer for increasing the effective area. Specifically, for 256 Mb DRAMs, a storage electrode having a one cylinder stacked structure is being widely used. Such a method is disclosed in U.S. Pat. Nos. 5,721,153, 5,817,555 and 5,759,894.
For manufacturing the above stacked-capacitors, a selective etching process for etching a structure of both silicon oxide and polysilicon material must be used. Conventionally, for selectively etching polysilicon in a composite layer having both polysilicon and silicon oxide, a mixed composition of carbon tetrachloride gas and argon gas, a mixed gas of CF.sub.4 and oxygen, CF.sub.3 Cl gas, and a mixed composition of fluoro-carbon type compound and chloride gas are utilized. On the other hand, carbon tetrafluoride gas, C.sub.2 F.sub.4 gas, and CHF.sub.3 gas are utilized for selectively etching silicon oxide.
However, distinct homogeneous layers of silicon oxide or polysilicon can be etched simultaneously. For example, U.S. Pat. No. 5,228,950 discloses a method of removing residues from oxide and silicon materials by using an etchant gas comprising NF.sub.3 as a main constituent.
Accordingly, in the conventional etching process, an etchant and etching equipment are selected based upon the type of material to be etched, such as polysilicon, oxide or metals. Preferably, for selectively etching layers near or adjacent to layers not to be etched, an etchant having a high selectivity for the layer to be etched is selected. In this respect, gate electrodes and bit-lines, which conventionally comprise polysilicon, are etched by utilizing polysilicon etching equipment, while silicon oxide etching equipment is used for etching insulating layers of hot temperature oxide (HTO) and BPSG, which conventionally comprise silicon oxide.
However, recently, as semiconductor devices become more highly integrated, the conventional etching process described above is becoming inadequate for more complicated processes. Particularly, in the process of manufacturing semiconductor devices, a composite layer comprised of a number of different materials such as polysilicon and silicon oxide is currently used in various components as opposed to a conventional single layer structure. Accordingly, the semiconductor manufacturing industry has been attempting to find a method of effectively etching composite layers comprising both polysilicon and silicon oxide.
FIGS. 1A to 1J are sectional views illustrating a manufacturing process of a conventional semiconductor device comprising a capacitor having a cylindrical shape.
Referring to FIG. 1A, on a semiconductor substrate 70 made from a semiconductor material such as silicon, a field oxide layer 75 for defining the active regions of various devices on the substrate 70 is formed by a local oxidation of silicon (LOCUS) method. On the active region defined by the field oxide layer 75, a gate oxide layer 80 is formed by thermal oxidation.
A first polysilicon layer and subsequently a first insulating layer made from silicon oxide are then formed on the surface of the substrate 70. The first polysilicon layer and first insulating layer are then etched to obtain gate electrodes 95 each having a polysilicon pattern 85 and an insulating layer pattern 90 on its respective gate oxide layer 80 or field oxide layer 75. Thereafter, utilizing the gate electrode 95 as an ion implantation mask, a low concentration impurity region on the semiconductor substrate 70 is formed by ion implanting a low concentration of impurity.
Then, a second insulating layer is formed on the substrate 70 by a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method utilizing high temperature oxide (HTO) or the like oxide material. The deposited second insulating layer is then etched by an anisotropic etching method to form a spacer 100 on the respective side walls of the gate electrodes 95.
Thereafter, utilizing the gate electrode 95 and the spacer 100 as an ion implantation mask, a transistor source/drain region 105 having a lightly doped drain (LLD) structure is formed by ion implanting a high concentration of impurity on the active region.
An insulating interlayer 87 comprising silicon oxide is then formed on the surface of the substrate 70 having gate electrode 95, followed by forming a hole in the insulating interlayer 87 to expose a portion of the common source/drain region 105 by a conventional photolithography process. Then, a metal layer filling the above hole is deposited on the surface of the insulating interlayer 87 by a sputtering method using aluminum or like metals, and a bit-line 89 as shown is formed by patterning the metal layer.
Then, a second insulating interlayer 160 comprising BPSG or PSG is formed by a low pressure chemical vapor deposition method or a plasma enhanced chemical deposition method. The surface of the second insulating interlayer 160 is planarized by a chemical mechanical polishing (CMP) method, in preparation for subsequent deposition and patterning processes.
Referring to FIG. 1B, a contact hole 107 for exposing a portion of the source/drain region 105 is formed by subjecting the first and second insulating interlayers 87 and 160 to a conventional photolithography process. The contact hole 107 is then filled to form a first conductive layer 165 on the surface of the second insulating interlayer 160. The first conductive layer 165 is formed by depositing a doped polysilicon using a low pressure chemical vapor deposition method.
Referring to FIG. 1C, the above first conductive layer 165 is then subjected to a CMP process or an etch-back process to form a contact 170 in the contact hole 107 communicating with the source/drain region 105.
Referring to FIG. 1D, on the common surface of the contact 170 and the second insulating interlayer 160, a sacrificial layer 115 comprising BPSG, PSG, USG, or the like oxide material is formed, followed by forming a photoresist film 120 on the surface of the sacrificial layer 115.
Referring to FIG. 1E, the photoresist film 120 formed on the surface of the sacrificial layer 115 is then subjected to a photo-process to form a photoresist pattern 120a, and using the photoresist pattern 120a as a mask, the sacrificial layer 115 is etched to form holes 125 for exposing the contact 170 and the second insulating interlayer 160 in their respective cell units.
Referring to FIG. 1F, after removing the photoresist pattern 120a, a continuous layer of second conductive layer 175 is formed on the surfaces of the contact 170 and second insulating interlayer 160 exposed by the hole 125 and on the sidewalls and the upper surface of the sacrificial layer 115. The second conductive layer 175 is formed by depositing impurity-doped polysilicon using a low pressure chemical vapor deposition method. As a result, the cells are formed with a well or a groove covered with a second conductive layer 175 made from polysilicon. Thereafter, an HSG silicon layer 150 is formed on the surface of second conductive layer 175 which is now formed on the sacrificial layer 115 and source/drain region 105. The HSG silicon layer is formed on the inner and bottom surfaces of the well of the second conductive layer 175 by a reduced pressure chemical vapor deposition method.
Referring to FIG. 1G, on the second conductive layer 175 now being covered with HSG silicon layer 150, a protective layer 155 is formed by a reduced pressure chemical deposition method utilizing undoped silicate glass (USG) having silicon oxide as its main constituent. The protective layer 155 which fills the well defined by the second conductive layer 175 is formed evenly, and serves to protect the HSG silicon layer 150 formed on the second conductive layer 175 during the subsequent etching process of forming storage electrodes.
Referring to FIG. 1H, the protective layer 155 is subjected to an etch-back process to leave behind a protective layer residue 155a, while exposing the remaining HSG silicon layer 150 and the second conductive layer 175 formed on the sacrificial layer 115. Here, oxide material-etching equipment and a dry-etching method utilizing plasma are used for the etch-back process, and the etching gas composition is adjusted to have a higher selectivity for the protective layer 155 comprising silicon oxide material and to have less selectivity for the HSG silicon layer 150 and the second conductive layer 175, both comprising polysilicon material. Appropriately, a gas etchant having C.sub.2 F.sub.4 gas, CHF.sub.3 gas, or CF.sub.4 gas as its main composition are utilized to have a higher selectivity for the protective layer 155 formed from silicon oxide material. Because the etch-back process is more active at the middle regions, the center portion of the well shows more etching in contrast to the peripheral region, leaving behind the protective layer residue 155a having a recessed center portion.
Referring to FIG. 1I, the semiconductor substrate 70 is then transferred to another etching equipment for etching the HSG silicon layer 150 and the second conductive layer 175 formed on the surface of the sacrificial layer 115, until the upper portion of the sacrificial layer 115 is exposed. Here, the etching is performed by polysilicon-etching equipment via a dry-etching method utilizing plasma, and the gas etchant is adjusted to have a higher selectivity for the HSG silicon layer 150 and the second conductive layer 175 both comprising polysilicon material, and to have a lower selectivity for the protective layer residue 155a and the sacrificial layer 115 both comprising silicon oxide material. For example, by utilizing a dry etchant composition mainly comprising chlorine gas which has a higher selectivity for polysilicon material, the HSG silicon layer 150 and the second conductive layer 175 can be selectively etched away. A cylindrical-shaped storage electrode 130 is formed on each unit cell, the storage electrodes 130 comprising a second conductive layer pattern 175a and an HSG silicon layer pattern 150a. Here, during the etching process of etching the second conductive layer 175 and the HSG silicon layer 150, the protective layer residue 155a is also partially etched simultaneously.
In the above etching process, after etching the horizontal portion of the second conductive layer 175, the vertical portion is also subsequently etched. As shown in FIG. 1I, the vertical etching is more active at the center portion than the peripheral region, causing the second conductive layer 175 to have a profile with a depressed center. Referring to FIG. 1J, by utilizing an etchant composition to completely remove all silicon oxide remaining on the semiconductor substrate 70, the sacrificial layer 115 and the protective layer residue 155a remaining in the well of the storage electrode 130 are removed by a wet-etching process. Then, on the surface of the storage electrode 130, a dielectric film 135 and subsequently a plate electrode 140 are formed to obtain a capacitor 145. Thereafter, a DRAM device is formed with a transistor and the capacitor 145 by the conventional semiconductor device manufacturing processes.
According to the above described process of manufacturing a semiconductor memory device, in the process of forming a storage electrode, the second conductive layer 175, which is covered with HSG silicon layer 150, and the protective layer 155 both comprise polysilicon material and are subjected to an etch-back process by utilizing two separate pieces of etching equipment (a silicon oxide-etching device and a polysilicon-etching device) using respective gas etchants.
Utilizing two such separate etching steps for the etch-back process renders an unsatisfactory surface profile. Specifically, when the protective layer 155 is etched first utilizing silicon oxide-etching equipment, the polysilicon-constituted second conductive layer 175 and HSG silicon layer are exposed while the protective layer 155 is being etched. In this state, because the etching process is more selective for the silicon oxide-constituted protective layer 155, the second conductive layer 175 and the HSG silicon layer 150 are etched less, resulting in an upward protrusion profile as shown by FIG. 1H. Further, in the subsequent process of selectively etching the second conductive layer 175 and the HSG silicon layer using polysilicon-etching equipment, because the polysilicon-constituted layers are etched more, the layers comprised of silicon oxide material and their neighboring portions protrude upward while the center portions of the polysilicon constituted layers show a profile having a depression.
FIG. 3A is an enlarged view of the area shown in the circle 3A of FIG. 11, and FIG. 3B is a sectional view illustrating the area of FIG. 3A after a process of wet-etching the sacrificial layer 115. Conventionally, the semiconductor substrates having the same or similar profile as the substrate 70 shown by FIG. 11 are later subjected to a wet-etching process to remove the sacrificial layer 115 and the protective layer residue 155a shown in FIG. 3A. In such a wet-etching process, shown by FIG. 3B, an HSG polysilicon particle H which occupies the uppermost portion of the HSG silicon layer as shown by FIG. 3A commonly detaches or falls off to form an electrical polysilicon bridge with the devices from the adjacent or neighboring capacitors, causing shorts and consequently lowering the yield of the semiconductor devices.
Such a polysilicon bridge may also be caused by a second conductive layer formed on the edge portion of the semiconductor substrates, and conventionally, an additional photolithography process is applied to remove the polysilicon formed on the edge of the semiconductor substrates.
FIGS. 2A to 2F are sectional views illustrating an additional photolithography process for processing the edge portion of the semiconductor substrate illustrated in FIGS. 1D to 1I.
Referring to FIG. 2A, after forming a sacrificial layer 115 comprising a silicon oxide material, a photoresist film 120 is formed as shown by FIG. 1D.
Referring to FIG. 2B, the photoresist film 120 is subjected to a conventional photo-process to form photoresist patterns 120a and 120b for forming a hole in each unit cell. Here, the photoresist pattern 120b which is formed to mainly occupy the edge portion of the semiconductor substrate is much larger in size than the photoresist pattern 120a formed on the region of the cells. Then, by utilizing the photoresist patterns 120a and 120b as an etching mask, the sacrificial layer 115 is etched to form a number of holes 125 to be utilized for eventually forming a capacitor. Here, by the photoresist pattern 120b occupying the edge portion, a sacrificial layer pattern 115a is formed on the edge portion of the semiconductor substrate.
Referring to FIG. 2C, after removing the photoresist patterns 120a and 120b by utilizing a stripping or ashing process, a second conductive layer 175 is formed on the common surface of the contact 170 and the second insulating interlayer 160 and on the whole surface of the sacrificial layer 115. Here, the second conductive layer 175 is also formed on the edge portion of the substrate and on the sacrificial layer pattern 115a located near the edge of the substrate. Then, an HSG silicon layer 150 is formed on the surface of the second conductive layer 175.
Referring to FIG. 2D, a protective layer 155 is formed on the surface of the HSG silicon layer 150 which covers the second conductive layer 175. The protective layer 155 is formed from USG (undoped silicate glass) constituted by silicon oxide material utilizing a low pressure chemical vapor deposition method.
Then, the protective layer 155 and the second conductive layer 175 are subjected to an etch-back process. Here, to prevent any polysilicon from remaining on the edge portion of the substrate after the etch-back process, portions of the protective layer 155 covering the edge of the substrate are first removed by an additional photolithography process prior to the etch-back process, as described in detail below.
Particularly, as shown in FIG. 2D, a second photoresist film 157 is formed by coating a photoresist on the surface of the protective layer 155. Then, as shown in FIG. 2E, the portion of the second photoresist film 157 which is on the edge of the substrate is removed to form a photoresist pattern 157a, by selectively light exposing and developing the edge portion of the semiconductor substrate. By forming this photoresist pattern 157a, a portion 155b of the protective layer 155 on the periphery of the substrate near the edge is exposed. Then, utilizing the photoresist pattern 157a as an etching mask, the peripheral protective layer 155b is removed by an etching process, as shown by the dotted line in FIG. 2E, to expose the peripheral portion of the HSG silicon layer located close to the edge of the substrate. Thereafter, by utilizing a wet-etching process with a polysilicon etchant, a portion of the second conductive layer 175a and a portion of the HSG silicon layer 150a, as shown by the dotted line, are removed. Then the second photoresist pattern 157a is removed by stripping process.
After the steps shown in FIG. 2E, the protective layer 155 is subjected to an etch-back process. Here, as shown in FIG. 2F, because the sacrificial layer 115 is also constituted by the same silicon oxide material which makes up the protective layer 155, a portion of the sacrificial layer 115a located on the edge of the substrate is simultaneously partially etched by the etch-back process. As a result of the above described processes, the peripheral protective layer 155b, a portion of the second conductive layer 175a, and a portion of the HSG silicon layer 150a, all being located on the periphery near to the edge of the substrate, have been removed.
Referring to FIG. 2G, utilizing the protective layer residue 155a as an etching mask, the remaining HSG silicon layer 150 and the second conductive layer 175 near to the edge of the substrate, covering the upper portion of the sacrificial layer 115, are etched-back until the upper portions of the sacrificial layer 115 and the sacrificial layer pattern 115a are exposed. As a result of this process, as shown, all portions of the HSG silicon layer 150 and the second conductive layer 175 formed on the periphery and very near to the edge of the substrate are now completely removed; hence, a formation of a silicon bridge can be prevented.
According to the method described above, in order to prevent the formation of a silicon bridge, prior to subjecting the protective layer and the second conductive layer to an etch-back process, the protective layer located at the periphery and on the edge of the substrate is preliminarily removed to expose the polysilicon formed at the same location. Once exposed, the polysilicon is then removed by a wet-etching process to render a semiconductor substrate free of polysilicon at its edge and peripheral region. For processing the edge of the substrate, the method is accompanied by a photoresist coating, development, and etching processes.